1. Field of the Invention
The present invention relates to a solid-state image sensor, a method of manufacturing the same, and a camera.
2. Description of the Related Art
A solid-state image sensor, such as a CCD sensor or a CMOS sensor, includes a plurality of pixels arranged in the imaging region. Each pixel includes a photoelectric converter and a transfer gate that forms a channel to transfer charges accumulated in the photoelectric converter to the signal output portion. The signal output portion can be a vertical CCD register in the CCD sensor or a floating diffusion connected to the gate of an amplification transistor in the CMOS sensor. For effective signal charge collection and dark current suppression, the photoelectric converter generally uses a buried photo diode, which includes a p+-type region in the surface of the semiconductor, an n-type region just under the p+-type region, and an n−-type region under the n region. The n−-type region that contacts the lower face of the p+-type region serves as a signal charge accumulation region.
The number of saturated electrons, that is, the saturated charge in the accumulation region is almost proportional to the product of the area of the accumulation region and the potential depth. However, as the potential deepens, electron transfer to the signal output portion becomes harder. Especially when the pixel area is small, it is difficult to ensure both a sufficient number of saturated electrons and adequate signal transfer performance.
Japanese Patent Laid-Open No. 2008-078302 discloses a structure in which a p+-type region, an n-type region, a p−-type region, and an n−-type region are arranged in the depth direction from the surface of the semiconductor substrate. In this structure, since the p−-type region is arranged in contact with the lower face of the n-type region serving as the accumulation region, the thickness of the n-type region is limited. Semiconductor theory states that the thinner n-type accumulation region could get the lower voltage necessary for depleting the n-type region, on the condition that the impurity concentration in the n-type accumulation region is adjusted to keep constant the saturation electrons. As the low depletion voltage makes it easy to transfer the signal charge, the limitation of the n-type region thickness could ensure both adequate saturation and the transfer performance.
However, in the structure disclosed in Japanese Patent Laid-Open No. 2008-078302, the potential gradient in the depleted n−-type region collecting the signal charge is small. This may decrease the sensitivity or increase crosstalk. In a structure in which a p-type region is arranged to isolate the pixels in the horizontal direction, especially when the pixel size is small, the p-type region acts to flatten the potential of the n−-type layer. Hence, the sensitivity decrease may be more conspicuous. That is, in the conventional pixel structure or the structure of Japanese Patent Laid-Open No. 2008-078302, it may be difficult to satisfy all the requirements of the saturated charge quantity, transfer performance, and sensitivity especially when the pixel size is small.